In today's rapidly advancing semiconductor manufacturing industry, the integrated circuit chips that form semiconductor devices include a multitude of conductive structures such as interconnect lines, contacts and vias. The performance of a semiconductor device depends upon device speed and there is an aggressive, continuing push to increase device speed and enhance device performance. The speed of a device is directly proportional and highly dependent upon the contacts and vias, collectively referred to as contact structures, formed between interconnection structures and the various semiconductor components and substructures. As such, various materials and combinations of materials have been used in an attempt to provide low-resistance contact structures and low-resistance interconnect structures. Moreover, as technologies advance, device features become smaller and smaller and the aspect ratios of the openings within which contacts, vias and other conductive structures are formed, becomes higher. This makes it more difficult to completely fill the contact or via openings in a void-free manner necessary to produce a suitably low contact or via resistance, using conventional technology. The reliability of a semiconductor device is also extremely critical and reliability can be degraded or compromised by poor contact i.e. high contact resistance.
A conventional structure commonly used as a contact between a metal layer and a further semiconductor device or used as a via between metal layers, is a tungsten plug with one or more barrier layers and other layers. Conventional contact structures are commonly formed by forming an opening in a dielectric layer, then forming a PVD, physical vapor deposition, barrier layer with an additional glue layer lining the opening prior to filling the opening with CVD tungsten, i.e. tungsten formed using a chemical vapor deposition, CVD, process. Barrier layers are utilized extensively in semiconductor device processing. Barrier layers are used at contact junctions between metal materials to prevent spiking between the metal materials. As the aspect ratio of single or dual damascene contact and via structures increases, it becomes increasingly difficult to obtain good step coverage using conventional PVD and CVD methods. The poor step coverage results in voids that increase the resistivity of the contact structure and degrade device performance. Additionally, as the size of the contact continues to decrease, the resistivity of the tungsten contact increases dramatically slowing down the semiconductor device and thereby degrading performance. As such, copper has been considered as a replacement for tungsten in contact and via structures but copper conventionally requires the initial formation of a PVD barrier layer followed by a seed layer formed in the opening before copper deposition takes place. As above, the shortcomings of forming a barrier layer using PVD processes include poor step coverage and an associated increase in resistance and a decrease in reliability.
It would therefore be desirable to produce conductive structures such as contacts, vias and conductive lines, with lows resistance and high reliability and which are scalable to the reduced geometries and high aspect ratios required in today's semiconductor manufacturing industry.